The proposed design showed superiority when compared with the conventional LFSR and related work in reducing power dissipation and area. The proposed 4-bit BS-LFSR achieved an active area of 1241.1588um2 and consumed only 53.8844nW with total power savings of 19.43%. The XOR function can also be viewed as part of the digital addition function in that XORs are used as the Sum portion of the simplest. A common linear function of single bits is the XOR. The BS-LFSR was designed in Mentor Graphic – TSMC Design Kit Environment using 130nm complementary metal oxide semiconductor (CMOS) technology. In digital signal processing, a linear-feedback shift register, or LFSR, is a shift register where the input bit is a linear function of its previous state. The pass transistor merged with transistor stack method yielded a better reduction in power dissipation compared to pass transistor design and NAND gate design. A feedback-with-carry shift register (FCSR) with 'Fibonacci' architecture is a shift register provided with a small amount of memory which is used in the feedback algorithm. In addition, three different architectures to enhance the feedback element used in BS-LFSR was explored. Here we will focus on the Galois LFSR form, not the Fibonacci LFSR. Linear feedback shift register Ask Question Asked 12 years, 10 months ago Modified 1 year, 2 months ago Viewed 30k times 11 Lately I bumped repeatedly into the concept of LFSR, that I find quite interesting because of its links with different fields and also fascinating in itself. To achieve low power dissipation, the proposed BS-LFSR introduced the stacking technique to reduce leakage current. For example, consider two 3-bit XOR based LFSRs with different tap selections ( Fig 2 ). In this paper, an enhanced BS-LFSR for low power application is proposed.

Bit swapping linear feedback shift register (BS-LFSR) is employed in a conventional linear feedback shirt register (LFSR) to reduce its power dissipation and enhance its performance.

3 bit linear feedback shift register